This invention relates to a controllable amplifier circuit comprising successively, in a cascode arrangement between a power supply voltage and ground, a control transistor having a control input for applying a gain control signal thereto and a field effect amplifier transistor for a controllable amplification of an input signal applied to a gate input, said control transistor varying the working point of the field effect amplifier transistor in the ohmic range depending upon the gain control signal, at least in a part of the control range of the gain control signal.
A controllable amplifier circuit of this type is known, inter alia, from Japanese Patent publication no. 62-187145.
In the known controllable amplifier circuit the cascode arrangement of the field effect amplifier transistor (FET) and the control transistor is realised by means of first and second field effect transistors (FETs), respectively of a two-port FET tetrode, hereinafter also referred to as an amplifier tetrode. The first FET amplifies a high-frequency input signal applied to its gate input, hereinafter referred to as the first gate. The gain factor of this first FET is dependent on its working point. This working point is controlled mainly by controlling the drain-source voltage. To this end, the second FET operating as a control transistor, varies the drain voltage of the first FET depending upon the gain control signal which is applied to the second gate, i.e. the gate input of the second FET. The gain of the first FET is maximal in an initial or uncontrolled state of the gain control. In this state the working point of the first FET is controlled by a maximum drain-source voltage in the saturation range. This is achieved at an initial maximum value of the gain control signal. Since the source voltage of the second FET approximately follows its gate voltage and is equal to the drain voltage of the first FET, a decrease of the gain control signal at least results initially in a decrease of the drain-source voltage and hence of the gain of the first FET. In the output characteristic, or I.sub.D -V.sub.DS characteristic of this first FET, such a decrease of the gain control signal results in a shift of its working point through the saturation range and towards the ohmic range.
In the case of a continuing decrease of the gain control signal, it reaches said part of the control range after it has passed a given value, hereinafter referred to as the threshold value. At this threshold value the first FET comes out of its saturated state. The first FET then has its working point in the transition range between the saturation range and the ohmic range, also referred to as the knee region. A decrease of the gain control signal in this part of the control range results in a much stronger decrease of the drain current I.sub.D of the FET tetrode than a comparable decrease of the gain control signal in the preceding part of the control range. Consequently, the gain of the first FET strongly decreases from this threshold value with a decreasing amplitude of the gain control signal. Since the gate-source voltage and hence the non-linearities do not change, the distortion and cross-modulation effects caused by these non-linearities in the first FET increase considerably with respect to the output signal amplitude.
To reduce these non-linearities, the source of the first FET in the known controllable amplifier circuit is connected to ground via a source resistor. Since the voltage across this source resistor varies with the drain current I.sub.D of the FET tetrode, a DC negative feedback is obtained which increases the gate-source voltage in the case of a decrease in gain. A certain degree of linearization is then obtained.
The extent of linearization increases with the value of the source resistor. However, the required power supply voltage also increases with the source resistance. In practice, limits are imposed on the value of the power supply voltage and particularly when the supply is provided by means of batteries, the required power supply voltage should be as low as possible. This imposes limits on the linearization of the known controllable amplifier circuit.